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Track Chair: Ayse Coskun, Boston University, US, Contact Topics Modeling and specification methodologies for complex HW-SW systems; requirements engineering; multi-domain/multi-criteria specifications; meta-modeling; design and specification languages; application and workload models; models of computation and their (static) analysis; concurrency and communication models; model- and component-based design; refinement and validation flows; modeling and analysis of functional and non-functional system properties; performance modeling; timing analysis; predictive and learning-based models; system-level platform and architecture models and simulation.High-level and system-level synthesis techniques; high-level design languages; system-level models for design and optimization; methods for HW-SW co-design and partitioning; control and data flow analysis; HW-SW interface and protocol communication synthesis; interface-based and correct-by-construction designs; high-level and system-level scheduling, allocation, and binding techniques; multi-objective optimization techniques (e.g., performance, power, reliability, security) for high-level and system design; platform-based and reuse-centric design methods and architectures; HW/SW design patterns for multi-processor system-on-chip (MPSo C); system-level design of heterogeneous computing systems.Modeling, circuit design, and design automation flows for future computing, including: non-CMOS logic based on emerging devices (e.g., carbon nanotube or graphene based FETs, TFETs, NWFETs, single electron transistors, NEMS etc.); alternative interconnect technologies (e.g., optical, RF, 3D, carbon nanotubes, graphene nanoribbons, spintronics, etc.); monolithic 3D integration (including TSV modeling and design space exploration).Modeling, circuit design, and design automation flows for future data storage systems, including non-CMOS memory (e.g., MRAM, STT-RAM, Fe RAM, PCRAM, RRAM, Ox RAM, quantum dots, etc.); memory-centric architectures (e.g., logic-in-memory, associative memories, non-volatile caches etc.); memory management techniques for emerging memories.Algorithms, techniques, and tools for modeling, estimating, or optimizing power consumption of electronic systems, applicable at all levels of the design (HW, SW, or system level), including: dynamic power management; leakage current minimization; design flows and circuit architectures for ultra-low power consumption; energy harvesting; battery modeling and design.Methods, techniques, and architectures for counteracting circuit and system variability due to manufacturing process, temperature, or aging effects, including: design-time and runtime temperature, variability, and reliability management of So Cs and multi-core platforms (both at HW and SW level); modeling and optimization approaches for manufacturing-induced or temperature variations; modeling and optimization methods targeting degradation mechanisms in emerging integration and manufacturing technologies (e.g., 3D stacking).

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